1. Field of the Invention
The present invention relates to digital integrated circuits, and, in particular, to timing-error detection in digital circuits.
2. Description of the Related Art
In recent years, circuit designers have investigated various approaches for predicting failures in integrated circuits (ICs). One such approach is known as critical-path performance monitoring. In conventional critical-path performance monitoring, a circuit designer identifies one or more signal paths that are deemed to be critical for the proper operation of an integrated circuit (known as “critical paths” or “critical data paths”), usually a path having a maximum delay. For a given circuit element within the critical path, the designer further identifies a target timing margin, i.e., a period of time before which a data signal transition should arrive at the circuit element, relative to a clock signal transition. A timing-monitor circuit (or “aging sensor”) is provided on the integrated circuit to monitor the timing of the signals in each critical path. As the integrated circuit ages over time, the actual timing of the signals in each critical path tends to degrade. When a timing-monitor circuit determines that the actual timing margin of a signal in a critical path is less than the target timing margin, one may anticipate that a circuit failure is likely to occur, and the integrated circuit may take steps to self-correct, e.g., by adjusting the clock frequency, the voltage supply, or even the body bias voltage of the transistors in the integrated circuit. See, e.g., Neil Savage, “Intel and ARM are Exploring Self-Correction Schemes to Boost Processor Performance and Cut Power,” Spectrum Online, February 2008, http://www.spectrum.ieee.org/feb08/5975, and Mridul Agarwal et al., “Circuit Failure Prediction and its application to Transistor Aging,” 25th IEEE VLSI Test Symposium, May 6-10, 2007, pp. 277-286, each of which is hereby incorporated by reference in its entirety.
FIG. 1 is a block diagram of an integrated circuit 100 that includes a critical path 102 and a timing-monitor circuit 110 described by Agarwal et al. Critical path 102 includes circuit elements 104, 106. Timing-monitor circuit 110 includes (i) a D-type flip-flop 118 inserted after circuit element 104 and before circuit element 106 in critical path 102, (ii) a delay element 114 having delay value TG equal to the target timing margin for this location along critical path 102 and connected to the output of the first circuit element 104, (iii) another D-type flip-flop 116 connected to the output of delay element 114, and (iv) an exclusive-OR (XOR) logic gate 122 connected to the outputs of flip-flops 118, 116.
Depending on the application, delay value TG will typically be in the range from several hundred picoseconds to several nanoseconds. Timing-monitor circuit 110 operates by delaying a copy of the signal 112 appearing at the output of circuit element 104 by delay value TG, latching the delayed signal at flip-flop 116, and comparing the output from flip-flop 116 via XOR logic gate 122 to the output signal 120 appearing at the output of flip-flop 118. Output signal 126 from XOR logic gate 122 is then latched into a timing failure indicator register 124, which produces output signal 128. Output signal 128 is then passed to a controller, which may adjust either the clock rate or a supply voltage for the integrated circuit, based on output signal 128.
As a first example, assuming that signal 112 comprises a data transition from a logic value 0 to a logic value 1 and that the setup time for flip-flop 116 is just satisfied (i.e., has zero timing margin), then the logic value 1 will be successfully latched into flip-flop 116 with clock CL. Since the 0-to-1 transition will arrive at input D of flip-flop 118 at some earlier time with respect to clock CL, flip-flop 118 will also successfully latch in the logic value 1. The XOR timing failure indicator register 126 will have a logic value 0, because both flip-flops have the same output values. This logic value 0 indicates that flip-flop 118 in the critical path has satisfied its setup time by at least the target timing margin set by delay value TG.
As a second example, where a 0-to-1 data transition in signal 112 occurs a short time later than in the above example (e.g., due to the aging of circuit elements in critical path 102 upstream of signal 112), flip-flop 118 may successfully latch in the logic value 1 with clock CL, while flip-flop 116 latches in the logic value 0 due to delay value TG. XOR timing failure indicator register 126 will now have a logic value 1, indicating that a setup violation has occurred in flip-flop 116 and that flip-flop 118 has a setup margin of less than delay value TG. As such, a timing failure will be more likely to occur, e.g., as the circuit continues to age.
Under certain circumstances, however, timing-monitor circuit 110 may give an erroneous indication that the timing for critical path 102 is satisfied, even though a setup violation may occur. In particular, if the 0-to-1 transition occurs later than in the second example above, flip-flops 116, 118 both may experience setup violations and incorrectly latch in a logic value 0. In this instance, the XOR timing failure indicator register 126 will incorrectly show a logic value 0, because it is unable to detect the case of setup violations in both flip-flops.
In addition to this susceptibility to give false negatives, timing-monitor circuit 110 has several other disadvantages. First, because only one delay element 114 is used, timing issues can be identified only with the resolution of delay value TG of that element.
Second, in order for timing-monitor circuit 110 to test the timing of critical path 102, some minimal amount of data activity must occur in critical path 102, in order to cause enough data transitions in signal 112 to produce timing failure (or success) indications. If there is little data activity in critical path 102, then delays in critical path 102 (e.g., due to aging) may arise but be undetected by timing-monitor circuit 110.
Third, timing-monitor circuits are typically added to an integrated circuit only after the physical design and static timing analysis (including the identification of critical paths) for the integrated circuit have been completed. When flip-flop 118 in timing-monitor circuit 110 is inserted into critical path 102, however, both the timing and loading of critical path 102 are impacted. As such, circuit loading and timing analysis likely need to be repeated after timing-monitor circuit 110 is placed, and the physical design may have to be changed to accommodate the timing-monitor circuit 110. Such changes may have a significant impact on the design schedule for the integrated circuit.